The present application generally relates to memory cells and, more particularly, to dynamic random access memory (DRAM) cells.
The demand for large-capacity, high-speed and low-power memory devices has been increasing. There are normally two kinds of memory devices, namely, static random access memory (SRAM) and dynamic random access memory (DRAM) devices. Although an SRAM can operate at very high speed, it may occupy a large area on a large-scale integration (LSI) because of its six-transistor (6T)-cell structure. Moreover, it may be difficult for an SRAM cell to be scaled down because of the issue of matching among cell transistors thereof. A DRAM cell, which consists of one transistor and one capacitor (1T/1C), may have a relatively small cell size and a relatively high operation speed. However, a conventional 1T/1C DRAM cell may face a problem in that as the device feature size shrinks, new material such as high dielectric constant film may be needed for a stacked capacitor or a high aspect ratio trench may be required for a trench capacitor combined with a vertical shape access transistor. To circumvent this, several approaches have been used. One of the approaches is the use of a gain cell including a stacked tunnel transistor. Another approach is a magnetic random access memory. However, the former may require a new device structure, and the latter may introduce new material into a metal-oxide-semiconductor (MOS) process, implying that it may take a long time for both to be phased in a productive large-scale memory.
In light of this situation, another kind of memory, called a capacitor-less 1T DRAM or a floating-body cell (FBC), has been provided. This new memory cell uses a floating-body of a partially depleted (PD) silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) as a storage node. Therefore, the 1T DRAM cell may not need a complicated storage capacitor, which means that the 1T DRAM cell may have a good process compatibility with logic devices.
FIG. 1A and FIG. 1B are schematic diagrams illustrating a prior art 1T DRAM cell 10 in different states. The 1T DRAM cell 10 includes a source region 11, a drain region 12, a gate region 13, a cell body 15, and a buried oxide (Box) layer 14, wherein the source region 11, the drain region 12, and the cell body 15 all include silicon. FIG. 1A schematically illustrates the 1T DRAM cell 10 in a logic “1” state while FIG. 1B schematically illustrates the 1T DRAM cell 10 in a logic “0” state. For the 1T DRAM cell 10 according to the prior art, the logic “1” state may be written by means of gate induced drain leakage (GIDL) or impact ionization (II). And the logic “0” state can be done by forward biasing of PN junction, which exists at source to body junction and drain to body junction. Therefore, the 1T DRAM cell 10 may sense whether the majority carriers (holes) accumulate in the floating-body as the threshold voltage (Vth) changes. The source is set to 0 volt, the drain is connected to a bit line, and the gate is connected to a word line. When excess holes exist in the floating-body and Vth lowers, the cell state may be regarded as “1”. On the other hand, when excess holes are swept out of the floating-body by a forward bias on the body-drain junction and Vth becomes higher, the cell state may be regarded as “0”. The drain current difference between “1” and “0” states can be sensed in the linear current region so as not to change the number of holes by the II current. By performing a read operation in the linear current region, the 1T-DRAM cell achieves the nondestructive read operation during a refresh interval.
The 1T DRAM cell does not need a complicated storage capacitor, which may save the cell size. However, it may be desirable to provide good memory data retention and/or sufficient writing speed for 1T DRAM cells.